1. Field of the Invention
The present invention relates to a semiconductor device including an NMOSFET for use in a level shift circuit, for example.
2. Description of the Related Art
For example, a drive circuit for a gate of an insulated-gate bipolar transistor (IGBT) on the side of a high side is configured using a semiconductor substrate 1 as shown in, for example, FIGS. 16 and 18.
This drive circuit, as shown in FIG. 19, includes two level shift circuits each of which is constituted of an NMOSFET 131 (or 132) and a resistor R and high side control logic 51 and a low side control logic 52 each of which is constituted of a CMOS logic, thereby acting as a circuit to drive gates of IGBTs 61 and 62. A high-voltage power integrated circuit that includes a level shift circuit for outputting a signal having a level thus shifted has been available conventionally (see U.S. Pat. No. 5,801,418, for example) typically for use in a CMOS logic of a circuit to drive a high side gate of an IGBT in a half-bridge connection by use of IGBTs as shown in FIG. 19. Note that a CMOS transistor shown in FIG. 16 and other drawings has an exemplary configuration that operates on a floating power source.
In FIGS. 16 and 18, a reference numeral 1 indicates a P− substrate, a reference numeral 2 indicates an N− epitaxial layer, a reference numeral 3 indicates a P region formed to reach the P− substrate 1 from a surface of the N− epitaxial layer 2, a reference numeral 104a indicates a P region formed in the surface of the N− epitaxial layer 2, and a reference numeral 104b indicates a P− region separately formed from the P region 104a in such a manner so as to conduct to the P+ region 3 (see FIG. 18).
Further, a reference numeral 5 indicates an N+ region formed in a surface of the P region 104a, a reference numeral 107a indicates an N+ region formed in the surface of the N− epitaxial layer 2 so as to be surrounded by the P− region 104b, a reference numeral 107b indicates an N+ region formed outside the P− region 104b, a reference numeral 8 indicates a P+ region formed in the surface of the P region 104a, a reference numeral 9 indicates a substrate electrode formed so as to be in contact with the P+ region 3, a reference numeral 10 indicates a source electrode formed so as to be in contact with the N+ region 5 and the P+ region 8, a reference numeral 11 indicates a gate electrode formed on an insulation film on the surface of the P region 104a sandwiched between the N+ region 5 and the N− epitaxial region 2, a reference numeral 12 indicates a drain electrode so as to be in contact with the N+ region 107a, and a reference numeral 13 indicates a floating power source electrode formed on the surface of the N+ region 107b. 
FIG. 16 shows an example of applying a double-resurf technology for equalizing a surface electric field and illustrates an extension (portion sandwiched between two dotted lines) of a depletion layer in a case where Vout has reached a maximum possible potential (≈Vh), to persuade that in this case the N− layer 2 and the P− region 4b are depleted simultaneously upon voltage application but a resultant depletion layer does not reach the above-described CMOS regions, so that the device can operate normally in a condition where its potential is kept high with respect to a substrate potential.
In a circuit configuration shown in FIG. 19, the NMOS transistor 131 or 132 is indispensable which transmits a logic signal based on an ordinary reference substrate potential to a logic circuit having a floating potential, so that in a provided planar configuration shown in FIG. 18, NMOS transistors are configured which respectively have cross-sectional structures shown in FIG. 16. In the drive circuit thus configured, when the NMOS transistor 131 is turned ON, a current flows through the resistor R, thereby giving rise to a difference in potential between V1 and Vd.
It is to be noted that although the N+ regions 107a and 107b are connected to each other with the N− epitaxial layer 2, the N− epitaxial layer 2 is depleted to produce a potential barrier of a depletion layer, which in turn cuts off an electron current.
However, in a conventional configuration shown in FIG. 16, such a problem occurs that when a voltage applied to V1 decreases, a non-depleted region occurs in the N− epitaxial layer 2 and has a current path (portion indicated as a resistor Rp in FIG. 17) formed in it.
This problem may lead to such a trouble that an effective value of a resistance of the resistor R is decreased, to disable normal transmission of a signal.
This problem is more serious in a case where a plurality of NMOS transistors is formed (whose top view is shown in FIG. 18 and circuit is shown in FIG. 19) because this JFET is formed between these NMOS transistors and extremely difficult to cope with.